The present invention relates to an electrically erasable programmable nonvolatile semiconductor memory device such as an EEPROM.
Recently a NAND cell type EEPROM has been proposed as one of the available electrically erasable programmable nonvolatile semiconductor memory devices. In this EEPROM, adjacent source and drain regions of a plurality of memory cells are connected in series, and these series-connected regions are connected to a bit line as one unit. Each of the memory cells has an n-channel MOSFET structure wherein a floating gate serve as charge storage layers and a control gate, which are formed one on another.
FIGS. 26A and 26B are a plan view and an equivalent circuit diagram illustrating one of NAND cells of a memory cell array. FIG. 27A is a cross-sectional view taken along line 27a--27a of FIG. 26A, and FIG. 27B is a cross-sectional view taken along line 27b--27b of FIG. 26A.
The memory cell array including the plural NAND cells is formed on a p-type silicon substrate (or p-type well) 71 surrounded with an element isolation oxide film 72. In this array, each of the NAND cells is constituted of eight memory cells M1 to M8 connected in series. In each of the memory cells, a floating gate 74 (74.sub.1, 74.sub.2, . . . 74.sub.8) is formed on the substrate 71 with a gate insulation film 73 interposed therebetween. Adjacent n-type diffusion layers 79 of the memory cells, which serve as source and drain regions, are connected in series.
First select gates 74.sub.9 and 76.sub.9 and second select gates 74.sub.10 and 76.sub.10 are provided on the drain and source sides of the NAND cell, respectively. The first select gates 74.sub.9 and 76.sub.9 and second select gates 74.sub.10 and 76.sub.10 are formed at the same time when the floating gate 74 and control gate 76 (76.sub.1 to 76.sub.8) are done. The first select gates 74.sub.9 and 76.sub.9 are connected to each other at a desired portion (not shown), as are the second select gates 74.sub.10 and 76.sub.10. The substrate on which the elements are formed is covered with a CVD oxide film 77, and a bit line 78 is provided thereon. The control gate 76 (76.sub.1 to 76.sub.8 =CG.sub.1 to CG.sub.8) serves as a word line, and the select gates 74.sub.9 and 76.sub.9, and 74.sub.10 and 76.sub.10 (SG.sub.1, SG.sub.2) are arranged in the row direction and each serves as a select gate line.
FIG. 28 illustrates an equivalent circuit of the memory cell array having NAND cells arranged in matrix. In this circuit, one source line is provided every 64 bit lines and connected through a contact to a reference potential wiring formed of aluminum, polysilicon or the like. The reference potential wiring is connected to a peripheral circuit. The control gates and the first and second select gates of the memory cell are arranged continuously in the row direction. Usually a group of memory cells to which the control gates are connected in common, is called one page, and a group of pages arranged between paired select gates on the drain (first select gate) and source (second select gate) sides is called one NAND block or simply one block. One page is constituted of, e.g., 256-byte (256.times.8) memory cells. Data is written to the memory cells of one page almost at once. One block is constituted of, e.g., 2048-byte (2048.times.8) memory cells. Data is erased from the memory cells of one block almost at once.
The NAND cell type EEPROM performs the following operation. In one NAND cell, data is written first to a memory cell located far away from the bit line. A voltage of 0V or a power supply voltage Vcc is applied to the bit line in accordance with the data. To write data "0" is called "0" write, and to write data "1" corresponding to Vcc is called "1" write. The power supply voltage Vcc is applied to a select gate for connecting the NAND cell to the bit line, and the ground potential 0V is applied to a select gate for connecting the NAND cell to the source line. At this time, 0V is applied from the bit line to a channel of the "0" write cell. Since, in the "1" write, the select gate connected to the bit line is turned off, the potential of a channel of the "1" write memory cell is Vcc-Vthsg (Vthsg is a threshold voltage of the select gate), resulting in a floating state.
After that, a boosted write voltage vpp (=about 20V) is applied to the control gate of a selected memory cell, and an intermediate potential Vpass (=about 10V) is applied to those of the other non-selected memory cells. Since the potential of the channel of the selected memory cell is at 0V when data is "0," a high voltage is applied between the channel and floating gate of the selected memory cell, with the result that electrons are injected from the channel into the floating gate by F-N tunneling and the threshold voltage of the selected memory cell is moved in the positive direction. When data is "1," the potential of the channel in the floating state is set to about 6V by capacitance coupling of the channel and the control gate, so that no electrons are injected from the channel into the floating gate.
The data stored in memory cells of each block are erased almost at the same time. In other words, for example, when a memory cell is formed within a p-type well provided in an n-type substrate, all the control and select gates of a block to be erased are set to 0V, and a boosted voltage VppE (=about 20V) to the p-type well and n-type substrate, with the result that electrons are emitted from the floating gate to the well and the threshold voltage of the memory cell is moved in the negative direction and, at this time, VppE is applied to the control and select gates of blocks which is not to be erased.
In the data readout operation, the bit lines are precharged and then set in a floating state. In this state, the control gate of a selected memory cell is set to 0V, the control and select gates of the other memory cells are each set to, e.g., 4.5V, and the source line is set to 0V to detect whether a current flows through the selected memory cells by an amount of variation in potential of the bit lines. More specifically, when data "0" (Vth&gt;0) is written to the memory cell, the memory cell is turned off and thus the bit lines remain at the precharge potential. On the other hand, when data "1" (Vth&lt;0) is written to the memory cell, the memory cell is turned on and thus the bit lines are dropped by .DELTA.V from the precharge potential. If the variations in the bit line potentials are sensed by a sense amplifier, data of the memory cell is read out.
Conventionally, when data "1" is written, the channel potential is set to an intermediate one by capacitance coupling of the control gate and channel. However, for example, when the capacitance of a diffusion layer (n.sup.+ region in FIG. 27) of a memory cell is large, the voltage of the channel is increased only by about 3V even though a voltage of 10V is applied to the control gate. Consequently, when a high voltage for writing data is applied to a selected control gate, a difference in potential between the channel and control gate of a memory cell connected to the control gate to write data "1" is widened, and data is written to the memory cell in error. It can thus be thought to apply a voltage of 10V or higher to a non-selected control gate. However, when the voltage to be applied to the non-selected control gate is simply heightened, the reliability of a memory cell, which is connected to the non-selected control gate and whose channel is set at a potential of 0V, is influenced adversely. Thus, the potential of the non-selected control gate cannot be increased.